{"id":4374,"date":"2018-02-26T14:27:00","date_gmt":"2018-02-26T13:27:00","guid":{"rendered":"https:\/\/ok2haz.ok2kld.cz\/ok2haz\/?p=4374"},"modified":"2023-01-29T09:05:31","modified_gmt":"2023-01-29T08:05:31","slug":"citac-s-gps-normalem-2-hw-zpracovani","status":"publish","type":"post","link":"https:\/\/ok2haz.ok2kld.cz\/ok2haz\/2018\/02\/citac-s-gps-normalem-2-hw-zpracovani\/","title":{"rendered":"\u010c\u00edta\u010d s GPS norm\u00e1lem \u2013 2. HW zpracov\u00e1n\u00ed"},"content":{"rendered":"\n

P\u0159i konstrukci \u010d\u00edta\u010de FC-1300 jsme zcela p\u0159e\u0161li od n\u00e1vrhov\u00e9ho programu Eagle Cadsoft k open-source n\u00e1vrhov\u00e9mu syst\u00e9mu KiCad EDA<\/a>. Nutno podotknout, \u017ee KiCad je n\u00e1strojem nejen srovnateln\u00fdm, ale dle na\u0161eho n\u00e1zoru v\u00fdrazn\u011b lep\u0161\u00edm ne\u017e zm\u00edn\u011bn\u00fd Eagle. Jeho \u201cnulov\u00e1\u201d po\u0159izovac\u00ed cena je u\u017e jen bonbonkem na dortu. Nulov\u00e1 p\u00ed\u0161u v \u00favozovk\u00e1ch proto, nebo\u0165 je t\u0159eba se s programem nau\u010dit a investovat tak sv\u016fj \u010das. V\u00fdsledek ale v\u00e1\u017en\u011b stoj\u00ed za to.
V KiCadu v\u0161e funguje spolehliv\u011b, stoj\u00ed za n\u00edm velk\u00e1 komunita v\u00fdvoj\u00e1\u0159\u016f. M\u00e1 \u0159adu pokro\u010dil\u00fdch funkc\u00ed. Velmi u\u017eite\u010dn\u00fd je nap\u0159\u00edklad adaptivn\u00ed routing, kdy p\u0159i ta\u017een\u00ed cesty na desce plo\u0161n\u00fdch spoj\u016f mohou ostatn\u00ed cesty nebo prokovy \u201cuh\u00fdbat\u201d nov\u011b veden\u00e9 cest\u011b.<\/p>\n\n\n\n

Stoj\u00ed rovn\u011b\u017e za zm\u00ed\u0148ku, \u017ee KiCad je hojn\u011b pou\u017e\u00edv\u00e1n a vlastn\u011b vze\u0161el z prost\u0159ed\u00ed evropsk\u00e9 organizace pro jadern\u00fd v\u00fdzkum \u2013 CERN<\/strong><\/a><\/p>\n\n\n\n

3D simulace v\u00fdsledn\u00e9 desky:<\/strong><\/p>\n\n\n\n

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Navr\u017eenou prototypovou desku jsem nechal vyrobit v PragoBoard (kusov\u00e1 cena v pool servisu 1200,-k\u010d za 1ks), desky dal\u0161\u00ed nech\u00e1me vyrobit v \u010d\u00ednsk\u00e9m Allpcb.<\/a><\/p>\n\n\n\n

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Modul desky \u010d\u00edta\u010de je navr\u017een pro vstupn\u00ed nap\u011bt\u00ed 12V, t\u00edmto nap\u011bt\u00edm je p\u0159\u00edmo nap\u00e1jen OCXO, extern\u00ed periferie na vstupn\u00edm modulu, silov\u00fd DC-DC m\u011bni\u010d U2 s LM2596.
Zbytek desky pak pracuje na nap\u011b\u0165ov\u00fdch \u00farovn\u00edch:
+5VA \u2013 pro analogov\u00e9 vstupn\u00ed OZ a d\u011bli\u010dku, z 12V pomoc\u00ed line\u00e1rn\u00edho stabiliz\u00e1toru U9 LM7805
-5VA \u2013 pro analogov\u00e9 vstupn\u00ed OZ, z +5VD v\u011btve pomoc\u00ed DC-DC m\u011bni\u010de MC34063
+5VD \u2013 pro silov\u00e9 nap\u00e1jen\u00ed LED displeje U2 \u2013 LM2596
+3,3V \u2013 pro zbytek logiky a CPU, z +5VD pomoc\u00ed AMS1117-3,3<\/p>\n\n\n\n

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Sch\u00e9ma:<\/h2>\n\n\n\n
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Vstupn\u00ed obvody:<\/h2>\n\n\n\n

Dlouze, p\u0159edlouze jsem hledal vhodn\u00fd \u010d\u00edta\u010d na vstup. Nejrychlej\u0161\u00ed obvody \u0159ady 74VHC393 jdou \u201cpouze\u201d do 170MHz, pak u\u017e by bylo t\u0159eba pou\u017e\u00edt d\u011bli\u010dku a zbyte\u010dn\u011b ztr\u00e1cet rozli\u0161en\u00ed. Po n\u011bkolikat\u00fddenn\u00edm hled\u00e1n\u00ed vhodn\u00e9ho obvodu jsem narazil na obvod MC100EP016A. To je synchonn\u00ed \u010d\u00edta\u010d s ECL logikou pracuj\u00edc\u00ed dle datasheet a\u017e do kouzeln\u00fdch 1,4GHz. V na\u0161em zapojen\u00ed pracuje skute\u010dn\u011b a\u017e do 1380MHz<\/strong>.
Pot\u0159ebuje v\u0161ak diferenci\u00e1ln\u00ed buzen\u00ed, to by asi \u0161lo nahradit jednoduch\u00fdm buzen\u00edm s um\u011blou zem\u00ed na druh\u00e9m dif. vstupu, ale riziko, \u017ee to vnese dal\u0161\u00ed mo\u017enou chybu, pop\u0159\u00edpad\u011b nebude fungovat v\u016fbec, jsme necht\u011bli podstupovat. Tak\u017ee jsem musel naj\u00edt vhodn\u00fd budi\u010d na vstup, kter\u00fd pot\u0159ebn\u00fd diferenci\u00e1ln\u00ed sign\u00e1l \u201cClock\u201d vyrob\u00ed. Vyu\u017eil jsem velmi rychl\u00fd kompar\u00e1tor MAX 9601. Tento obvod dovede zpracov\u00e1vat\/generovat periodick\u00fd sign\u00e1l s maxim\u00e1ln\u00ed frekvenc\u00ed odpov\u00eddaj\u00edc\u00ed 4Gbps, tak\u017ee bychom m\u011bli vyu\u017e\u00edt cel\u00fd rozsah vstupn\u00edho \u010d\u00edta\u010de. M\u011b\u0159en\u00fd sign\u00e1l X p\u0159iv\u00e1d\u00edme na neinvertuj\u00edc\u00ed vstup (pin 11) diff. OZ MAX9601. Na invertuj\u00edc\u00ed vstup p\u0159ivedeme ss nap\u011bt\u00ed \u201cTrigger\u201d pot\u0159ebn\u00e9 velikosti, toto nap\u011bt\u00ed generujeme 12bit DA p\u0159evodn\u00edkem v CPU.
Hystereze opera\u010dn\u00edho zesilova\u010de odpov\u00edd\u00e1 rezistoru R19 (12k), ta je nastaviteln\u00e1 v intervalu 2-65mV (12k odpov\u00edd\u00e1 hysterezi 20mV).
OZ m\u00e1 rozd\u011blen\u00e9 napajen\u00ed, symetrick\u00e9 Vcc\/Vee pro vlastn\u00ed OZ a Vcco pro nap\u00e1jen\u00ed v\u00fdstupn\u00edch budi\u010d\u016f. Budi\u010de v\u00fdstup\u016f Q a \/Q jsou v zapojen\u00ed s otev\u0159en\u00fdm emitorem, tak\u017ee pot\u0159ebuj\u00ed pull-down resistory (R14+R16 a R29+R30).
V datasheet k MC100EP016A jsou nakreslen\u00e9 pull-up, co\u017e je chyba.
<\/em>Co nejbl\u00ed\u017ee pouzdra OZ jsou filtra\u010dn\u00ed\/blokovac\u00ed kondenz\u00e1tory. 1\u03bcF jako BULK a pak 100nF+1nF jako blokovac\u00ed pro vykr\u00fdv\u00e1n\u00ed kr\u00e1tkodob\u00fdch proudov\u00fdch \u0161pi\u010dek.<\/p>\n\n\n\n

Druh\u00fd opera\u010dn\u00ed zesilova\u010d U5A zaji\u0161\u0165uje dostate\u010dn\u00e9 p\u0159esn\u00e9\/strm\u00e9 sp\u00edn\u00e1n\u00ed sign\u00e1lu GATE, po kter\u00fd \u010d\u00edta\u010d \u010d\u00edt\u00e1. V\u00fdstupem Q (pin 1) sp\u00edn\u00e1 LE vstup opera\u0159n\u00edko zesilova\u010de U5B a \/CE vstup asynch. 8 bit \u010d\u00edta\u010de MC100EP016A.<\/p>\n\n\n\n

V\u00fdstupem z \u010d\u00edta\u010de U7 je 8-mi bitov\u00fd sign\u00e1l, kde bit D0 m\u00e1 nejni\u017e\u0161\u00ed v\u00e1hu (LSB) a vstupn\u00ed sign\u00e1l CLK d\u011bl\u00ed dv\u011bma. D7 m\u00e1 pak nejv\u011bt\u0161\u00ed v\u00e1hu (MSB) a d\u011bl\u00ed CLK 256-ti. To znamen\u00e1, \u017ee p\u0159i vstupn\u00edm kmito\u010dtu 1380MHz je na D7 kmito\u010det f\/256, tedy cca 5,4MHz, co\u017e u\u017e spolehliv\u011b zvl\u00e1dne klasick\u00e1 logika. Tou je 8-mi bitov\u00fd \u010d\u00edta\u010d 74HC393D, jeho v\u00fdstup ji\u017e jde p\u0159\u00edmo do CPU, kde navazuj\u00ed \u010d\u00edta\u010de dal\u0161\u00ed. Celkem takto z\u00edsk\u00e1me bin\u00e1rn\u00ed \u010d\u00edta\u010d a\u017e do  XXX bit\u016f.
Jednotliv\u00e9 v\u00fdstupy z \u010d\u00edta\u010d\u016f U7 a IC8 vedou do multiplexer\u016f 74HC151 IC15+IC16. Takto m\u016f\u017eeme p\u0159e\u010d\u00edst bitov\u00fd stav po skon\u010den\u00ed m\u011b\u0159en\u00ed (GATE).<\/p>\n\n\n\n

\u010casov\u00e1 z\u00e1kladna<\/h2>\n\n\n\n

Srdcem \u010dasov\u00e9 z\u00e1kladny je dvojit\u011b vyh\u0159\u00edvan\u00fd krystalov\u00fd oscil\u00e1tor (OCXO) Trimble 34310. Jeho v\u00fdstup kmit\u00e1 na 10MHz a pomoc\u00ed lad\u00edc\u00edho pinu ho lze rozla\u010fovat o cca \u00b1 2Hz, nap\u011b\u0165ov\u00e1 z\u00e1vislost je cca 1,5Hz\/V. T\u011bchto 10MHz natvarujeme v IC2. Pot\u00e9 ho vyd\u011bl\u00edme 10-ti pomoc\u00ed IC4A(74HC390D) a takto z\u00edskan\u00fd 1MHz sign\u00e1l spolu s 1MHz v\u00fdstupem generovan\u00fdm pomoc\u00ed GPS p\u0159ivedeme na vstupy XOR hradla. Takto m\u016f\u017eeme srovn\u00e1vat jejich f\u00e1zi a velmi p\u0159esn\u011b<\/strong> \u201cdoladit\u201d n\u00e1\u0161 m\u00edstn\u00ed krystalov\u00fd oscil\u00e1tor. T\u00edmto dok\u00e1\u017eeme vyu\u017e\u00edt kr\u00e1tkodobou p\u0159esnost GPS (Cesiov\u00e9 hodiny) a vynikaj\u00edc\u00ed dlouhodobou p\u0159esnost OCXO Trimble oscil\u00e1toru. Celkov\u00e1 p\u0159esnost 10MHz sign\u00e1lu \u010dasov\u00e9 z\u00e1kladny m\u016f\u017ee dosahovat stability a\u017e 2\u00d710-12 <\/sup>Hz (0,002 PPB). 1MHz \u010dasov\u00e9 z\u00e1kladny se v kask\u00e1d\u00e1ch d\u00e1le d\u011bl\u00ed op\u011bt v\u017edy 10ti. Takto z\u00edsk\u00e1me sign\u00e1ly o kmito\u010dtu 100Hz, 10Hz, 1Hz, 100mHz, 10mHz, 1mHz, ze kter\u00fdch ud\u011bl\u00e1me pulzy se st\u0159\u00eddou 1\/10 pomoc\u00ed NAND hradel (IC14 + IC19). Ty jsou vyvedeny do multiplexeru \u010dasov\u00e9 z\u00e1kladny.  V\u00fdstupn\u00ed pulz je tedy v 90% \u010dasu v log 1 (doba m\u011b\u0159en\u00ed \u2013 GATE) a 10% \u010dasu v log 0, kdy se p\u0159e\u010dtou a vynuluj\u00ed v\u0161echny \u010d\u00edta\u010de pomoc\u00ed CPU. V dal\u0161\u00ed m\u011b\u0159\u00edc\u00ed period\u011b se pak v\u0161e opakuje.<\/p>\n\n\n\n

N\u00e1sleduj\u00edc\u00ed video ukazuje zav\u011b\u0161en\u00ed PLL. Konkr\u00e9tn\u011b ve studen\u00e9m stavu OCXO,  tak\u017ee cel\u00e1 stabilizace trv\u00e1 cca 30s, proto\u017ee se nah\u0159\u00edv\u00e1 a t\u00edm p\u00e1dem rozla\u010fuje krystal. Na displeji voltmetru jde vid\u011bt zes\u00edlen\u00e9 lad\u00edc\u00ed nap\u011bt\u00ed (na C6) z v\u00fdstupu integra\u010dn\u00edho \u010dl\u00e1nku R18+C24. To se m\u011bn\u00ed v rozsahu 2-7,5V, kde osciluje v z\u00e1vislosti na st\u0159\u00edd\u011b v\u00fdstupu IC3B.<\/p>\n\n\n\n

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